Subsystem Verification Test - SSV

Test Description and Objectives

The objective of this test is to validate the correct operations of the P/L2 L-band RFI monitoring payload board layout, the quality of the data acquisition process, as well as the deployment and operation metrics of the Helical antenna. This test is meant to be performed both upon each new board assembly, as many of the errors discovered with this test are manufacturing-related and thus repeatable, as well as after any environmental test on the same board.

Requirements Verification

IDDescriptionStatus
M-0700The L-band receiver antenna will be omnidirectional, operate in the 1-2 GHz band and feature a reflection coefficient greater than 6 dBs.Ok
M-0710The L-band receiver antenna will be contained inside the satellite's allowed space envelope during launch and capable and controlled deployment once in orbitTBC
M-0720The L-band receiver front end will be compatible with the rest of the satellite in terms of power requirements and data exchange and storage capabilities.TBC
M-0730The L-band receiver front end will attain a 5 MHz or better frequency resolution.TBC

Test Set-Up

For performing this test, the following items are required:

test_set_up.jpg

In what follows the pinout of the P/L2 board will be explained. It is worth mentioning that the vertical pinout is shared by all boards of the PQ, so in case an OBC board is used, the connection can easily be done by simply mounting the 2 PCBs together using the vertical connectors. The pins used for this test are the folowing:

Connector indexPin positionNameDescription
J11SDA1I2C data bus 1 (reserved for payloads)
J12SCL1I2C clock bus 1 (reserved for payloads)
J19GNDGlobal Ground pin
J110VCCGlobal supply line (3.3V but not for P/L2)
J27GNDGlobal Ground pin
J210GNDGlobal Ground pin
J32PH6+Y photodiode pin (post amplification)
J36P/L_PowerPoL - controlled supply line (3.1 V)
J48DACOBC STM32 Digital-to-Analog output pin
J49ADCOBC STM32 Analog-to-Digital input pin

They can be located as follows in the vertical top (left) & bottom (right) views shown below:

PL2_bot_top_pins.png

Next up, the steps for the connections will be presented. They need to be replicated whenever a new test sub-section is performed, unless stated otherwise.

A light mounting is recommended as not to fully latch the pins which will make subsequent separation of the boards difficult. If however, for any reason, vertical mounting is not feasible OR if a Nucleo Board is chosen to be used instead of the OBC&COMMS board, then the connection of all pins shown above except VCC and GND should be done with male-female jumper cables, using oscilloscope probe endings to better latch to the P/L2 male vertical pins.

As the payloads are duty-cycled consumers whose activation needs to be strictly controlled, their supply is done through a PoL (point of load) switch located on the OBC board that, upon activation with a GPIO (General purpose Input/Output) pin of the STM32, enables the 3.3V permanent voltage line of the PocketQube to supply the P/L board through the P/L_Power pin. As a result, during this test, as this SSV aims at testing the payload under the same conditions as those encountered in orbit, the powering has been chosen to be done the nominal way, from the 3.3V VCC all the way through the OBC-controlled Pol, through the P/L_Power pin and into the actual payload board. It warrants mentioning however that, if someone would like to test exclusively the P/L2 board OR if the Nucleo Board approach has been chosen, direct powering through the P/L_Power pin is possible (in which case the power supply is directly connected to the latter pin, with the VCC pin not seeing use).

For details on STM32 operation, please refer to the OBC page within ³Cat-NXT Design chapter. Before continuing from this point, the reader should be able to operate the STM at least in what regards the I2C bus, ADC input and DAC output, as well as flash the newest version of the software.

After a test session is completed, regardless of the length of the hiatus, one should proceed to disable the signal generator and power supply (in this order), disconnect all the cables (very gently in the case of the U.FL and MS156 terminations), power off all equipment and safely store all cables in their designated bags, terminations apart, and place the item under test in an antistatic bag equipped with a silica bag.

Pass/Fail Criteria

This test will be considered passed if all of the following actions are performed succesfully:

Test Plan (By Subblocks)

Before moving towards the testing of the whole subsystem, in order to single out possible errors, the payload's isolated segments will be tested a part, starting for simplicity with those which do not require a STM32 (be it a Nucleo Board or the OBC&COMMS board) to be verified.

5V booster

The 5V booster, in the form of LT3048, is needed to augument the line voltage of 3.3 V of the PocketQube to 5 V in order to correctly supply the LEE2-6+ LNA. The testing procedure for it is listed below:

RF chain Low Noise Amplifier (LNA)

In the form of the LEE2-6+, fully explained in the appropiate P/L page, under the ³Cat-NXT Design chapter, the LNA is supposed to provide a gain between 20.6 dB (at 1 GHz) and 18.9 dB (at 2 GHz) over the L-band. To test this feature, a signal will be introduced at the receiver's input, and sampled from the first RF chain probe. The procedure is as follows:

The MS156 probes act like an electrically closed circuit when in nominal state, but disconnect the subsequent circuit when probed. This means that probing cuts elements further on the transmission line from the input, in this case anything past the J6 probe: bandpass filter, tuner, IF chain, etc...

Bandpass filter

The BFCG162W bandpass filter's function is to preselect the signal within a range indicated by the manufacturer to be between 950 MHz and 2200 MHz, with an insertion loss of lower than 3 dB in-band and higher than 20 dB out-of-band. These characteristics can be tested as follows:

Downconversion tuner

The downconversion of this receiver is done using the I2C controlled MAX2121 VSSAT tuner, from the 1-2 GHz RF chain to the 70 MHz IF chain, by applying a frequency sweep. Worth mentioning is that the task software verification is only subject to verification in the functional sense in this test, and it is explained in detail in ... Additionally, it is the last item of this receiver's front end to allow separate verification of sorts, as the subsequent IF chain is a differential line with no probing point, followed by the adaptation network of the RSSI and the RSSI itself. Therefore, the steps to follow are:

Photodiode Opamp

One unrelated functionality of the P/L2 board is also to house a photodiode corresponding to the +Y axis of the ADCS sensor module. It is placed on the TOP part of the board, and connected to an operational amplifier in non-inverting configuration designed to amplify its signal by a factor of 20 in order to make it more easily read by the OBC's ADC. The testing procedure is:

Test Plan (Full subsystem)

From this point the document is a stub.

Having tested and isolated possible errors as much as possible in a bit-by-bit manner in the previous section, a full subsystem test will now be performed.

Test Results

Description of the Test results (photos, tables, etc) with interpretation.

5V booster test:

RF chain LNA test:

Bandpass filter:

Downconversion tuner:

Photodiode Opamp:

Full subsystem test:

Anomalies

List of deviations to the Test Specification and Procedure and non-conformances witnessed during the test campaign, including a brief description, the close-out status and reference to the relevant reports.

Conclusions

Verified requirements (and within which part of the test), close-out judgement (compliance status) and rationale, statement of open issues and possible remediating actions


Revision #1
Created 15 November 2024 18:02:26 by roger.almirall
Updated 15 November 2024 18:02:50 by roger.almirall